Field
The disclosed technology relates generally to nonvolatile memory devices, and more particularly to ferroelectric non-volatile memory devices.
Description of the Related Technology
Some memory devices, e.g., embedded non-volatile memory devices, include floating gate-based devices, which store electrostatic charge in the floating gate. To address scalability issues associated with floating gate-based devices, some embedded non-volatile memory devices include electron trap-based devices, e.g., polysilicon-oxide-nitride-oxide-silicon (SONOS) devices, which store electrostatic charges in the gate stack, e.g., in the oxide-nitride-oxide, instead of a floating gate. For both types of devices, the reading operation is performed by sensing the current trough a channel, which is modulated by the stored charge.
Injecting charge into and from a floating gate or a charge trapping layer (e.g., the nitride layer in SONOS devices, which is electrically insulating) may be performed under relatively high voltages (e.g., between 10V and 20V). The high voltage operations programming (e.g., write and erase) operations may be undesirable, especially embedded memory applications, because the relatively high voltages are usually provided by high voltage circuitry, e.g., large charge pumping circuits, which may be integrated on-chip, and include large high voltage transistors. In addition, writing and erasing are much slower than reading in floating gate-based or charge trapping layer-based devices. Moreover, building-in a charge pump on-chip adds a substantial number of processing steps, which renders embedded non-volatile memory a very high-cost memory solution. For these reasons, the use of embedded non-volatile memory devices has been limited to applications where the added cost and/or process/design complexity are outweighed by the need, e.g., in security, smart cards, automotive microcontrollers, among other applications.
Another non-volatile memory which has attracted great attention from the relevant industry as a good candidate for both memory and switching applications is the ferroelectric field-effect transistor (FeFET) memory. Some FeFET memory devices resemble a standard metal-oxide-semiconductor FET (MOSFET). Unlike a standard MOSFET, however, the gate oxide dielectric is replaced by a ferroelectric material for a FeFET memory device. By modulating the gate electrode, e.g. for n-MOS by applying a positive (Vcc) or negative voltage (−Vcc) inversion or accumulation, respectively, of the channel occurs at the ferroelectric-semiconductor (channel) interface, while writing/erasing and thereby switching the FeFET on (“1” state) or off (“0” state). As the gate voltage is released, the device remains in its state. These states correspond to the so-called remnant polarization states +Pr and −Pr, respectively. The bistable state of a ferroelectric can thus be programmed as binary information (“1” or “0”). This is due to the displacement of charges which is inherent to the crystal structure of the ferroelectric material and does not disappear in the absence of the electric field or gate voltage applied. Without being bound to any theory, these considerations render ferroelectric materials suitable for use in low-power non-volatile memories that use lower program/erase voltages (typically +/−4V). In addition, these low program/erase voltages are obtained while having similar or better performance metrics compared to floating gate-based or charge trapping layer-based memories, e.g., faster writing and erasing times.
However, the adoption of the FeFET has been substantially hampered for several reasons. Some of these reasons were addressed when the ferroelectric phase in doped orthorhombic HfO2 was discovered. However, due to yjr presence of a depolarization field, which is due to the low permittivity of the silicon channel (about 12), there can be a non-zero electric field that is applied to materials in contact with the ferroelectric material even under the retention condition when no voltage is applied. As a consequence, there may also be a corresponding electric field over the ferroelectric material which is persistent and opposite to the polarization (by Gauss' law). The resulting induced electric field can disadvantageously work against the polarization and hence depolarize the cell, which can result in a gradual erasure of a cell that has been programmed. Therefore, there is a need for novel and improved FeFET memory devices that address these and other limitations of FeFETs.
One way to remove this depolarization field is to use a pinch-off ferroelectric memory cell, e.g., a pinch-off ferroelectric FET. The pinch-off FET comprises a relatively highly doped n-type semiconductor channel on a n-type substrate, which will remain in accumulation mode even in the retention condition when no voltage is applied. In other words, the pinch-off FET is normally in a switched-on (state “1”) state without an external voltage. According to embodiments of the disclosed technology the channel length and/or doping used may be chosen such that the device can be pinch-off properly and provides the desired pinch-off voltage. However, when reading the cell state, i.e. the stored “1” or “0” data, from such a pinch-off ferroelectric FET, a negative gate bias (=read voltage) needs to be applied to the gate electrode in order to modulate the current and distinguish between a “1” and a “0” state. In a classical read-out scheme, this read voltage is placed between the two threshold voltage levels (programmed and erased), in order to have a current in one state and no current in the other one. In a pinch-off ferroelectric FET, however, such a scheme would correspond to a depleted state and an accumulation state. The depleted state would again introduce a depolarization field which again will cause the cell to lose its charge when reading it for a prolonged period of time.